>>17790
It's just how their field evolved, same as with math notation and other historical things.
Anyway, your latch, you may remember "combinatorial" and "sequential" logic disciplines.
When you're thinking about it from a combinatorial point of view, you pretend this is just simple timeless logical math, such as logical expressions like (A&~B)&(~A&B), you can just do your truth table or whatever, you can use all the usual logic theorems and methods (karnaugh maps, venn diagrams, or whatever else you may prefer) to find equivalent expressions.
So you're basically abstracting away everything else that happens in the actual reality of building the circuit and only care about its logical value, in the mathematical sense, you can use all kinds of transformation formulas and so on.
However, if we take a step back, we may realize that we're skipping many many details about the practical implementation of this, one detail is still quite relevant even if we still abstract from the rest of the analog matters: delay.
Let's take your NOR gate up there, or even the wire, in the case of the NOR gate, physically it could be made of transistors and wires (for example), each of those elements do not operate on 1s and 0s, they have voltages applied to some terminals and those voltages will cause changes at other terminals, since this is a physical process, it will take some time for the "output" to change, it doesn't go from 1 to 0 instantly, or from 0 to 1, it goes through intermediate rises and falls. What if your input wasn't even a full 1 or 0, but let's say 0.5 or 0.7 of that voltage? It will have a well determined behavior in most cases, the behavior sometimes won't even be that stable either! Even in the case of a simple wire, EM waves propagate at the speed of light, but for a long enough wire, you will start seeing all kinds of non-trivial (transmission line) behavior.
Note that a logic gate usually is not just your 2 inputs and one output, it will often also involve 2 power supply terminals for a positive (or negative) voltage source/supply and a drain/ground, in a typical gate implemented with let's say MOSFETs (as used in a typical IC), the voltage at the inputs is applied to the transistor's gates, the gate physically consists of a conductor and an oxide (insulator), then inbetween the source and drain we have a channel (source and drain are doped), the point here is that there's no(t much) current passing from the gate and (source/drain), the MOSFET gate mostly acts to create an electrical field which itself will pull or push charges in the channel, such that current can pass more easily or not pass at all, basically it's like if you had a resistor whose value you changed through the gate voltage (very simplified description, the actual channel is a doped semiconductor though, so the behavior is not the same as you would have if it was a metal wire), but in this simplified description, you could imagine that if you made the gate turn off, it's as if you set a huge gigaohm resistor there and prevented the circuit from completing, thus source and drain would not be connected (much), similarly if it was on, it was as if you connected the source and drain. In practice those transistors are not ideal and they don't conduct as well in the on and off state and in modern practice people use design methodologies like CMOS where even for a simple invertor (~ = NOT), you have 2 transistors (NMOS and PMOS), such that when the output is meant to be 0, it ends up taking it from the GND, and when it's 1 it takes it from the supply, with half of the circuit being "off" in typical operation - but you know, there will be an intermediate state, when one transistor opens and the other closes, and in that moment both will be conducting! In fact that's where most of the power dissipation comes in real chips - the fact that the state changes and for at least a moment it conducts - usually state will be made to change with the clock in typical synchronous circuit designs. In typical CMOS designs if inputs didn't change, you would typically not have power dissipation as long as the output itself as also connected as input to some other mosfet gate (thus it would hit the oxide and no current would "pass" through, only the electric field would change).
Okay, enough with the analog electronics, the important thing you may have noticed is that your gate will have unstable output for some time, meaning that inbetween you applying your input voltages, the output will not be correct/stable except after some time, also if the inputs themselves are not quite proper 0s or 1s, again, you may see weird behavior at the output - these are ultimately analog circuits!
So in the sequential logic discipline we still ignore most of the analog stuff but we don't forget that there's a delay until the output is stable.
Let's consider your simple SR latch. R - reset, S - set. Let's say S is 1, R is 0. the expected behavior is that the output (Q) must become 1 and ~Q must become 0 (as far as the definition of the SR latch is concerned)
We can look at the lower NOR: ~(1 OR X) = ~1 = 0, so we know that ~Q becomes 0 from this and is fed back to the input of R (again with a delay),
Let's consider the higher NOR now: ~(0 OR X) = ~X, so the output will be whatever ~Q was but negated, so it basically becomes Q. In the earlier case ~Q was 0, so Q is 1.
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